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The data recovery state machine processes samples and ultimately that produces valid output bits. The first step in the data recovery state machine consists of creating seven edge detect signals by pair-wise. The data recovery state machine starts rising edge and the falling edge samples to produce. In the process, the falling-edge signals are also moved into the clock domain. The state machine is implemented in a dual port block RAM, shared by two channels. A control signal controls the period of time which are accumulated. Data recovery state machine is generated for each channel. The period of Data recovery state machine is determined by the constant.

The state machine uses the edge information provided by the delay lines to adjust POS. A Data recovery state machine is included where the transitions are described with case and if statements. In the structural version the state machine is implemented in a block RAM. While both could be simulated and synthesized, the first one is intended for simulation and the second one for synthesis. The simulation version of the state machine is in a more readable format. This format is used for debugging and/or modifying the state machine behavior. While this version can be synthesized, it is not efficient since it would map into a large number of slices. For synthesis, use the block RAM since it is initialized with data producing exactly the same functionality as the behavioral version.

Data recovery state machine can be used for simulation and synthesis. Changes in the state machine functionality are made in the behavioral section. This method enables the implementation of any state machine behavior with the same number of inputs and outputs using the same low number of logic resources without affecting the device utilization, routing, and timing performance. The output elastic buffer converts the 1 bit 622 Mb/s data stream into a 5 bit 124.4 MHz output or 8-bit 77 MHz output. Each channel has own 16 5-bit word buffers. The initial state of the buffer is half full and the largest possible phase offset is accommodated before overrun or under run occurs. Data recovery state machine describes how to modify the reference designs given different input specifications.

The Data recovery state machine input is used to insert an extra delay at the input of the delay chain and shift all eight sampling points to a different bit area. Always pair the tiles, each pair shares a block RAM. It is possible to locate these block RAMs in the two block RAM columns inside the RPM tile area to create a very compact design without wasted resources. Directed routing errors point to placement inconsistencies. There is a timing budget issue when the data path is moving from the CLK0 domain to CLK180 domain at 311 MHz. In order to meet timing, a transparent latch is inserted in the path crossing the two clock domains. This latch adds a half clock cycle into the timing budget.

Data recovery state machine guarantee placement and routing of the design, it must be implemented in a larger device. High speed parallel bus interfaces, data recovery techniques using asynchronous data capture is quickly becoming a necessity. Asynchronous data capture is an alternative method of performing data recovery without the use of a DCM.

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